Invention Grant
- Patent Title: Power-rail ESD protection circuit with ultra low gate leakage
- Patent Title (中): 电源轨道ESD保护电路具有超低门极泄漏
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Application No.: US11987222Application Date: 2007-11-28
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Publication No.: US07755871B2Publication Date: 2010-07-13
- Inventor: Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
- Applicant: Ming-Dou Ker , Chin-Hao Chen , Ryan Hsin-Chin Jiang
- Applicant Address: TW Jhonghe
- Assignee: Amazing Microelectronic Corp.
- Current Assignee: Amazing Microelectronic Corp.
- Current Assignee Address: TW Jhonghe
- Agency: Stites & Harbison, PLLC
- Agent Juan Carlos A. Marquez, Esq.
- Main IPC: H02H9/04
- IPC: H02H9/04

Abstract:
An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
Public/Granted literature
- US20090135533A1 Power-rail ESD protection circuit with ultra low gate leakage Public/Granted day:2009-05-28
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