发明授权
US07759727B2 Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology 失效
用于屏蔽隧道电路和浮栅的方法和装置,用于在通用CMOS技术中集成浮栅参考电压

  • 专利标题: Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology
  • 专利标题(中): 用于屏蔽隧道电路和浮栅的方法和装置,用于在通用CMOS技术中集成浮栅参考电压
  • 申请号: US11639658
    申请日: 2006-12-14
  • 公开(公告)号: US07759727B2
    公开(公告)日: 2010-07-20
  • 发明人: Alexander KalnitskyJohn M. Caruso
  • 申请人: Alexander KalnitskyJohn M. Caruso
  • 申请人地址: US FL Palm Bay
  • 专利权人: Intersil Americas Inc.
  • 当前专利权人: Intersil Americas Inc.
  • 当前专利权人地址: US FL Palm Bay
  • 代理商 Donald L. Bartels
  • 主分类号: G11C16/04
  • IPC分类号: G11C16/04
Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology
摘要:
A method and corresponding structure for shielding a floating gate tunneling element. The method comprises disposing a floating gate over a gate oxide using standard CMOS processing in two active areas defined by first and second doped well regions formed in a substrate surrounded by field oxide, and forming a floating gate shield layer so as to enclose the floating gate. The floating gate includes a first floating gate portion over an active area in the first doped well region and a second floating gate portion over the active area in the second doped well region. The first floating gate portion is substantially smaller than the second floating gate portion so as to enable adequate voltage coupling for Fowler-Nordheim tunneling to occur between the first doped well region and the first floating gate portion. The direction of tunneling is determined by high voltage application to one of the doped well regions.
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