Invention Grant
- Patent Title: Multilayer wiring structure and method of manufacturing the same
- Patent Title (中): 多层布线结构及其制造方法
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Application No.: US11908731Application Date: 2006-03-02
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Publication No.: US07765686B2Publication Date: 2010-08-03
- Inventor: Akishige Murakami , Ikue Kawashima , Yoshikazu Akiyama
- Applicant: Akishige Murakami , Ikue Kawashima , Yoshikazu Akiyama
- Applicant Address: JP Tokyo
- Assignee: Ricoh Company, Ltd.
- Current Assignee: Ricoh Company, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2005-070227 20050314; JP2005-143590 20050517; JP2005-306592 20051021
- International Application: PCT/JP2006/304528 WO 20060302
- International Announcement: WO2006/098207 WO 20060921
- Main IPC: H05K3/20
- IPC: H05K3/20

Abstract:
A method of manufacturing a multilayer wiring structure is disclosed. The method comprises a step of forming a via post on a first metal wiring element, a step of printing an interlayer insulation film on the first metal wiring element, with use of a screen mask having a non-ejection area slightly larger than a head of the via post, such that the interlayer insulation film has an upper surface at the level lower than the head of the via post, while generally aligning the non-ejection area with the head of the via post, a step of curing the interlayer insulation film, and a step of forming a second metal wiring element in contact with the via post on the interlayer insulation film such that the first metal wiring element and the second metal wiring element are connected through the via post.
Public/Granted literature
- US20090025215A1 MULTILAYER WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2009-01-29
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