One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell

Invention Grant

US07767519B2 One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell 有权

Title translation: 一个晶体管/一个电容器动态随机存取存储器（1T / 1C DRAM）单元

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Patent Title: One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell
Patent Title (中): 一个晶体管/一个电容器动态随机存取存储器（1T / 1C DRAM）单元
Application No.: US12006061

Application Date: 2007-12-28
Publication No.: US07767519B2

Publication Date: 2010-08-03
Inventor: Brian S. Doyle , Dinesh Somasekhar , Robert S. Chau
Applicant: Brian S. Doyle , Dinesh Somasekhar , Robert S. Chau
Applicant Address: US CA Santa Clara
Assignee: Intel Corporation
Current Assignee: Intel Corporation
Current Assignee Address: US CA Santa Clara
Agency: Ryder, Lu, Mazzeo and Konieczny, LLC
Agent Douglas J. Ryder
Main IPC: H01L21/8242
IPC: H01L21/8242

One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell

Abstract:

In general, in one aspect, a method includes forming a semiconductor fin. A first insulating layer is formed adjacent to the semiconductor fin. A second insulating layer is formed over the first insulating layer and the semiconductor fin. A first trench is formed in the second insulating layer and the first insulating layer therebelow. The first trench is filed with a polymer. A third insulating layer is formed over the polymer. A second trench is formed in the third insulating layer, wherein the second trench is above the first trench and extends laterally therefrom. The polymer is removed from the first trench. A capacitor is formed within the first and the second trenches.

Abstract(Chinese):

通常，一方面，一种方法包括形成半导体鳍片。第一绝缘层邻近半导体鳍形成。在第一绝缘层和半导体鳍上形成第二绝缘层。在第二绝缘层和第一绝缘层中形成第一沟槽。第一个沟槽与聚合物一起提交。在聚合物上形成第三绝缘层。第二沟槽形成在第三绝缘层中，其中第二沟槽在第一沟槽之上并且从其横向延伸。从第一沟槽去除聚合物。在第一和第二沟槽内形成电容器。

Public/Granted literature

US20090166701A1 One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell Public/Granted day:2009-07-02

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8242	.........动态随机存取存储结构（DRAM）