Invention Grant
- Patent Title: Methods of forming vertical transistor structures
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Application No.: US11486524Application Date: 2006-07-13
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Publication No.: US07767525B2Publication Date: 2010-08-03
- Inventor: H. Montgomery Manning , Kunal R. Parekh , Cem Basceri , Gurtej S. Sandhu
- Applicant: H. Montgomery Manning , Kunal R. Parekh , Cem Basceri , Gurtej S. Sandhu
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.
Public/Granted literature
- US20060258087A1 Methods of forming vertical transistor structures Public/Granted day:2006-11-16
Information query
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