Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer

Invention Grant

US07767546B1 Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer 失效

Title translation: 低成本制造双盒背栅硅绝缘体晶片，在背栅层中内置浅沟槽隔离

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Patent Title: Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer
Patent Title (中): 低成本制造双盒背栅硅绝缘体晶片，在背栅层中内置浅沟槽隔离
Application No.: US12352071

Application Date: 2009-01-12
Publication No.: US07767546B1

Publication Date: 2010-08-03
Inventor: Robert H. Dennard , David R. Greenberg , Amian Majumdar , Leathen Shi , Jeng-Bang Yau
Applicant: Robert H. Dennard , David R. Greenberg , Amian Majumdar , Leathen Shi , Jeng-Bang Yau
Applicant Address: US NY Armonk
Assignee: International Business Machines Corporation
Current Assignee: International Business Machines Corporation
Current Assignee Address: US NY Armonk
Agency: Cantor Colburn LLP
Agent Vazken Alexanian
Main IPC: H01L21/30
IPC: H01L21/30

Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer

Abstract:

A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

Abstract(Chinese):

用于制造集成电路器件的半导体晶片结构包括体基片; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在所述下绝缘层上的导电层，所述导电层还具有形成在其中的一个或多个浅沟槽隔离（STI）区域; 形成在所述导电层和所述一个或多个STI区域上的蚀刻停止层; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。还公开了随后的有源面积电平STI方案，结合半导体层上的前栅极形成。

Public/Granted literature

US20100176453A1 LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER Public/Granted day:2010-07-15

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）