Invention Grant
US07768062B2 Combined volatile and non-volatile memory device with graded composition insulator stack
有权
组合易失性和非易失性存储器件，具有分级成分绝缘子堆叠
- Patent Title: Combined volatile and non-volatile memory device with graded composition insulator stack
- Patent Title (中): 组合易失性和非易失性存储器件，具有分级成分绝缘子堆叠
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Application No.: US12422580Application Date: 2009-04-13
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Publication No.: US07768062B2Publication Date: 2010-08-03
- Inventor: Arup Bhattacharyya , Kie Y. Ahn , Leonard Forbes
- Applicant: Arup Bhattacharyya , Kie Y. Ahn , Leonard Forbes
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded SiC—GeC—SiC composition. A charge blocking layer is formed over the tunnel insulator. A trapping layer of nano-crystals is formed in the charge blocking layer. In one embodiment, the charge blocking layer is comprised of germanium carbide and the nano-crystals are germanium. The thickness and/or composition of the tunnel insulator determines the functionality of the memory cell such as the volatility level and speed. A gate is formed over the charge blocking layer.
Public/Granted literature
- US20090200602A1 COMBINED VOLATILE AND NON-VOLATILE MEMORY DEVICE WITH GRADED COMPOSITION INSULATOR STACK Public/Granted day:2009-08-13
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