Invention Grant
- Patent Title: Drain extended MOS transistor with increased breakdown voltage
- Patent Title (中): 漏极扩散MOS晶体管具有增加的击穿电压
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Application No.: US11758451Application Date: 2007-06-05
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Publication No.: US07768068B1Publication Date: 2010-08-03
- Inventor: Kevin Jang , Bill Phan , Helmut Puchner
- Applicant: Kevin Jang , Bill Phan , Helmut Puchner
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L29/735
- IPC: H01L29/735

Abstract:
A semiconductor topography and a method for forming a drain extended metal oxide semiconductor (DEMOS) transistor is provided. The semiconductor topography includes at least a portion of an extended drain contact region formed within a well region and a plurality of dielectrically spaced extension regions interposed between the well region and a channel region underlying a gate structure of the topography. The channel region of a first conductivity type and the well region of a second conductivity type opposite of the first conductivity type. In addition, the plurality of dielectrically spaced extension regions and the extended drain contact region are of the second conductivity type. Each of the plurality of dielectrically spaced extension regions has a lower net concentration of electrically active impurities than the well region. Moreover, the extended drain contact region has a greater net concentration of electrically active impurities than the well region.
Information query
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