Invention Grant
- Patent Title: Semiconductor integrated circuit and wafer having diffusion regions differing in thickness and method for manufacturing the same
- Patent Title (中): 具有厚度不同的扩散区域的半导体集成电路和晶片及其制造方法
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Application No.: US11220716Application Date: 2005-09-08
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Publication No.: US07768094B2Publication Date: 2010-08-03
- Inventor: Toshihiko Iinuma
- Applicant: Toshihiko Iinuma
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JPP2005-111195 20050407
- Main IPC: H01L23/58
- IPC: H01L23/58
Abstract:
A semiconductor integrated circuit includes a rectangular low speed circuit area including a low speed circuit comprising a low speed transistor having a first source extension region and a first drain extension region, and a rectangular high speed circuit area adjacent to the low speed circuit area and including a high speed circuit comprising a high speed transistor having a second source extension region and a second drain extension region thinner than the first source and drain extension regions.
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