Invention Grant
- Patent Title: Shallow trench isolation process utilizing differential liners
- Patent Title (中): 使用差分衬套的浅沟槽隔离工艺
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Application No.: US12538008Application Date: 2009-08-07
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Publication No.: US07768095B2Publication Date: 2010-08-03
- Inventor: Srinath Krishnan
- Applicant: Srinath Krishnan
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: H01L29/93
- IPC: H01L29/93
Abstract:
A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.
Public/Granted literature
- US20090294896A1 SHALLOW TRENCH ISOLATION PROCESS UTILIZING DIFFERENTIAL LINERS Public/Granted day:2009-12-03
Information query
IPC分类:
