Invention Grant
- Patent Title: Integrated low inductance interconnect for RF integrated circuits
- Patent Title (中): 用于射频集成电路的集成低电感互连
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Application No.: US11473470Application Date: 2006-06-23
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Publication No.: US07768098B2Publication Date: 2010-08-03
- Inventor: Thomas R. Apel
- Applicant: Thomas R. Apel
- Applicant Address: US OR Hillsboro
- Assignee: TriQuint Semiconductor, Inc.
- Current Assignee: TriQuint Semiconductor, Inc.
- Current Assignee Address: US OR Hillsboro
- Main IPC: H01L29/00
- IPC: H01L29/00
Abstract:
An interconnect path configured for use in RFICs and configured to reduce inductance at the input of an array of cells, and also at the output of the array of cells. According to one preferred embodiment of the present invention, a multi-layered interconnect formed by at least two metal layers separated by dielectric medium is provided. The metal layers are closely spaced and separated by a desirable dielectric to achieve an interconnect having a characteristic inductance (Zo) that is much lower than typical microstrip transmission lines formed by a metal trace over the semiconductor substrate or a dielectric stack that includes the semiconductor substrate. The low Zo line provides much less inductance per unit length.
Public/Granted literature
- US20070296057A1 Integrated low inductance interconnect for RF integrated circuits Public/Granted day:2007-12-27
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