Invention Grant
- Patent Title: Semiconductor device including multi-layered interconnection and method of manufacturing the device
- Patent Title (中): 包括多层互连的半导体器件及其制造方法
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Application No.: US11250530Application Date: 2005-10-17
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Publication No.: US07768127B2Publication Date: 2010-08-03
- Inventor: Masaki Yamada , Hideki Shibata
- Applicant: Masaki Yamada , Hideki Shibata
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2003-407888 20031205
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
The semiconductor device includes a semiconductor substrate, and a multi-layer wiring portion including insulating layers and wiring layers alternately stacked one on another on a main surface of the semiconductor substrate. All of the wiring layers are made of a same basis metal, at least one of the wiring layers contains an additive element, and a concentration of the additive element is lower on an upper layer side than that on a lower layer side.
Public/Granted literature
- US20060244144A1 Semiconductor device including multi-layered interconnection and method of manufacturing the device Public/Granted day:2006-11-02
Information query
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