Invention Grant
- Patent Title: Interconnect structure and method for semiconductor device
- Patent Title (中): 半导体器件的互连结构和方法
-
Application No.: US12368598Application Date: 2009-02-10
-
Publication No.: US07768134B2Publication Date: 2010-08-03
- Inventor: Yoshiaki Shimooka , Tadashi Iijima
- Applicant: Yoshiaki Shimooka , Tadashi Iijima
- Applicant Address: US CA Irvine
- Assignee: Toshiba America Electronic Components, Inc.
- Current Assignee: Toshiba America Electronic Components, Inc.
- Current Assignee Address: US CA Irvine
- Agency: Banner & Witcoff, Ltd.
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.
Public/Granted literature
- US20090146290A1 Interconnect Structure and Method for Semiconductor Device Public/Granted day:2009-06-11
Information query
IPC分类: