Invention Grant
- Patent Title: Under voltage lock out circuit and method
- Patent Title (中): 欠压锁定电路和方法
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Application No.: US12345493Application Date: 2008-12-29
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Publication No.: US07768247B2Publication Date: 2010-08-03
- Inventor: Yoshikazu Sasaki , Tetsuro Hashimoto , Isao Yamamoto
- Applicant: Yoshikazu Sasaki , Tetsuro Hashimoto , Isao Yamamoto
- Applicant Address: JP
- Assignee: Rohm Co., Ltd.
- Current Assignee: Rohm Co., Ltd.
- Current Assignee Address: JP
- Agency: Cantor Colburn LLP
- Priority: JP2006-129866 20060509
- Main IPC: H02H3/24
- IPC: H02H3/24 ; G05F5/00

Abstract:
An under voltage lock out circuit which monitors an input voltage and executes a predetermined sequence when the input voltage satisfies a predetermined condition may include a voltage comparison unit which compares the input voltage and a predetermined threshold voltage, and outputs a comparison signal; a logic circuit which receives the comparison signal output from the voltage comparison unit and a start-up signal instructing start-up of an equipment mounted with the under voltage lock out circuit, and asserts a sequence control signal when start-up is instructed by the start-up signal in a state the input voltage is higher than the threshold voltage; and a sequence circuit which executes a predetermined sequence when the sequence control signal is asserted, wherein the predetermined threshold voltage is switched according to the sequence control signal.
Public/Granted literature
- US20090108827A1 UNDER VOLTAGE LOCK OUT CIRCUIT AND METHOD Public/Granted day:2009-04-30
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