Invention Grant
- Patent Title: High impedance, high parallelism, high temperature memory test system architecture
- Patent Title (中): 高阻抗,高并行度,高温记忆测试系统架构
-
Application No.: US11689585Application Date: 2007-03-22
-
Publication No.: US07768278B2Publication Date: 2010-08-03
- Inventor: Romi O. Mayder
- Applicant: Romi O. Mayder
- Applicant Address: SG Singapore
- Assignee: Verigy (Singapore) Pte. Ltd.
- Current Assignee: Verigy (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Holland & Hart, LLP
- Main IPC: G01R31/02
- IPC: G01R31/02

Abstract:
An electronic device for use with a probe head in automated test equipment. The device includes a plurality of semiconductor devices arranged to provide at least one driver/receiver pair where the driver portion of the driver/receiver pair is configured to transmit a signal to at least one device under test and the receiver portion of the driver/receiver pair is configured to receive a signal from the at least one device under test. Each of the plurality of semiconductor devices is fabricated using either a silicon-on-insulator (SOI) or metal-on-insulator (MOI) technology and has a thickness less than about 300 μm exclusive of any electrical interconnects. The at least one driver/receiver pair is adapted to mount directly to the probe head.
Public/Granted literature
- US20080191683A1 HIGH IMPEDANCE, HIGH PARALLELISM, HIGH TEMPERATURE MEMORY TEST SYSTEM ARCHITECTURE Public/Granted day:2008-08-14
Information query