Invention Grant
US07768278B2 High impedance, high parallelism, high temperature memory test system architecture 有权
高阻抗,高并行度,高温记忆测试系统架构

High impedance, high parallelism, high temperature memory test system architecture
Abstract:
An electronic device for use with a probe head in automated test equipment. The device includes a plurality of semiconductor devices arranged to provide at least one driver/receiver pair where the driver portion of the driver/receiver pair is configured to transmit a signal to at least one device under test and the receiver portion of the driver/receiver pair is configured to receive a signal from the at least one device under test. Each of the plurality of semiconductor devices is fabricated using either a silicon-on-insulator (SOI) or metal-on-insulator (MOI) technology and has a thickness less than about 300 μm exclusive of any electrical interconnects. The at least one driver/receiver pair is adapted to mount directly to the probe head.
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