Invention Grant
- Patent Title: Level shift circuit
- Patent Title (中): 电平移位电路
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Application No.: US12133124Application Date: 2008-06-04
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Publication No.: US07768308B2Publication Date: 2010-08-03
- Inventor: Masato Maede , Naoki Nojiri , Masahiro Gion , Shinji Kinuyama , Daisuke Matsuoka , Shiro Usami
- Applicant: Masato Maede , Naoki Nojiri , Masahiro Gion , Shinji Kinuyama , Daisuke Matsuoka , Shiro Usami
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2003-421155 20031218; JP2004-330249 20041115
- Main IPC: H03K19/094
- IPC: H03K19/094

Abstract:
In a level shift circuit, the threshold voltage of N-type high-voltage transistors, to whose gates the voltage of a low-voltage supply VDD is applied, is set low. An input signal IN powered by the low-voltage supply VDD is input to the gate of an N-type transistor by way of an inverter. Therefore, even if the potentials at nodes W3 and W4 exceed the voltage of the low-voltage supply VDD, reverse current flow from the nodes W3 and W4 via parasitic diodes within the inverters into the low-voltage supply VDD is prevented. A protection circuit, composed of N-type transistor whose respective gates are fixed to the low-voltage supply VDD, is disposed between the two N-type high-voltage transistors N5, N6 and two N-type low-voltage transistors N1, N2 for receiving the complementary signals IN and XIN, thereby preventing the breakdown of those N-type complementary-signal-receiving transistors.
Public/Granted literature
- US20080238481A1 LEVEL SHIFT CIRCUIT Public/Granted day:2008-10-02
Information query
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