Invention Grant
- Patent Title: Process variation tolerant sense amplifier flop design
- Patent Title (中): 过程变化容忍感觉放大器触发器设计
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Application No.: US11943455Application Date: 2007-11-20
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Publication No.: US07768320B1Publication Date: 2010-08-03
- Inventor: Ge Yang , Hwong-Kwo Lin , Charles Chew-Yuen Young
- Applicant: Ge Yang , Hwong-Kwo Lin , Charles Chew-Yuen Young
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson & Sheridan, LLP
- Main IPC: G01R19/00
- IPC: G01R19/00 ; G11C7/00 ; H03F3/45

Abstract:
One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.
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