Invention Grant
US07768332B2 Waveform generation apparatus, setup cycle correction method and semiconductor test apparatus
失效
波形发生装置,设置周期校正方法和半导体测试装置
- Patent Title: Waveform generation apparatus, setup cycle correction method and semiconductor test apparatus
- Patent Title (中): 波形发生装置,设置周期校正方法和半导体测试装置
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Application No.: US11811514Application Date: 2007-06-11
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Publication No.: US07768332B2Publication Date: 2010-08-03
- Inventor: Kenji Tamura
- Applicant: Kenji Tamura
- Applicant Address: JP Tokyo
- Assignee: Advantest Corp.
- Current Assignee: Advantest Corp.
- Current Assignee Address: JP Tokyo
- Agency: Muramatsu & Associates
- Priority: JP2007-141990 20070529
- Main IPC: G06F1/04
- IPC: G06F1/04 ; H03K3/00

Abstract:
Spurious noise that occurs in the vicinity of a carrier can be removed even when a high-resolution cycle is set, thereby realizing low jitters in a high-precision variable clock signal. Cycle data that is set by a pattern generator in a waveform generation apparatus (a semiconductor test apparatus) is corrected in such a manner that spurious noise that occurs in a carrier of a high-precision variable clock is produced at a position far from the carrier in terms of frequency. As a result, the spurious noise can be assuredly removed by a phase-locked loop circuit, thereby realizing low jitters in the high-precision variable clock signal.
Public/Granted literature
- US20080297222A1 Waveform generation apparatus, setup cycle correction method and semiconductor test apparatus Public/Granted day:2008-12-04
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