An integrated circuit (IC) having selectable memory elements is provided. The IC includes a logic array block (LAB) disposed within the IC. A plurality of logic elements, having look-up tables functioning as the selectable memory elements is included in the LAB. Within a logic element, a data path that shares multiplexers and drivers when the look-up tables of the logic elements are operated as one of a memory element or a combinational logic device is provided. In addition, a write address decoder is interconnected with the plurality of logic elements through a write bus.