Invention Grant
- Patent Title: Systems and methods for reducing the effects of ADC mismatch
- Patent Title (中): 减少ADC失配影响的系统和方法
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Application No.: US12111294Application Date: 2008-04-29
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Publication No.: US07768437B2Publication Date: 2010-08-03
- Inventor: Viswanath Annampedu , Venkatram Muddhasani
- Applicant: Viswanath Annampedu , Venkatram Muddhasani
- Applicant Address: US PA Allentown
- Assignee: Agere Systems Inc.
- Current Assignee: Agere Systems Inc.
- Current Assignee Address: US PA Allentown
- Agency: Hamilton, DeSanctis & Cha
- Main IPC: H03M1/36
- IPC: H03M1/36

Abstract:
Various embodiments of the present invention provide systems and methods for utilizing a plurality of potentially mismatched analog to digital converters. For example, a method for adaptively processing a variety of input signals is disclosed. The method includes providing an adaptive loop circuit, and a first and second circuit pairs. The first circuit pair includes a first analog to digital converter and first register, and the second circuit pair includes a second analog to digital converter and a second register. An input signal is received and an event status is received. The event status initially indicates that the input signal includes data associated with a first event and subsequently indicates that the input signal includes data associated with a second event. The first circuit pair to drive the adaptive loop circuit when the first event is indicated, and the second circuit pair to drive the adaptive circuit when the second event is indicated.
Public/Granted literature
- US20090267819A1 Systems and Methods for Reducing the Effects of ADC Mismatch Public/Granted day:2009-10-29
Information query
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