Invention Grant
US07768518B2 Enabling multiple instruction stream/multiple data stream extensions on microprocessors
有权
在微处理器上启用多个指令流/多个数据流扩展
- Patent Title: Enabling multiple instruction stream/multiple data stream extensions on microprocessors
- Patent Title (中): 在微处理器上启用多个指令流/多个数据流扩展
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Application No.: US11528121Application Date: 2006-09-27
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Publication No.: US07768518B2Publication Date: 2010-08-03
- Inventor: Jamison Collins , Perry Wang , Bernard Lint , Koichi Yamada , Asit Mallick , Richard A. Hankins , Gautham Chinya
- Applicant: Jamison Collins , Perry Wang , Bernard Lint , Koichi Yamada , Asit Mallick , Richard A. Hankins , Gautham Chinya
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F15/80
- IPC: G06F15/80

Abstract:
Embodiments described herein disclose a system for enabling emulation of a MIMD ISA extension which supports user-level sequencer management and control, and a set of privileged code executed by both operating system managed sequencers and application managed sequencers, including different sets of persistent per-CPU and per-thread data. In one embodiment, a lightweight code layer executes beneath the operating system. This code layer is invoked in response to particular monitored events, such as the need for communication between an operating system managed sequencer and an application managed sequencer. Control is transferred to this code layer, for execution of special operations, after which control returns back to originally executing code. The code layer is normally dormant and can be invoked at any time when either a user application or the operating system is executing.
Public/Granted literature
- US20080077909A1 Enabling multiple instruction stream/multiple data stream extensions on microprocessors Public/Granted day:2008-03-27
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