Invention Grant
US07768842B2 Semiconductor memory device voltage generating circuit for avoiding leakage currents of parasitic diodes 失效
半导体存储器件电压产生电路,用于避免寄生二极管的漏电流

Semiconductor memory device voltage generating circuit for avoiding leakage currents of parasitic diodes
Abstract:
A voltage generating circuit for semiconductor memory devices for use in avoiding the occurrence of leakage currents associated with parasitic diodes is presented. The circuit controls and stabilizes the generation of a fedback negative voltage to prevent parasitic diode malfunctions by a in a wordline driver. The voltage generating circuit includes a controller being fedback the negative voltage and detecting a potential difference between backbias voltage provided to a substrate of the cell and the negative voltage to generate a control signal. The voltage generating circuit also includes a voltage generator being fedback the negative voltage to detect a level thereof, and which subsequently generates and provides the negative voltage in response to the detected results of the negative voltage and the control signal.
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