A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.