Invention Grant
- Patent Title: On-chip characterization of noise-margins for memory arrays
- Patent Title (中): 内存阵列噪声裕度的片上特性
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Application No.: US11935205Application Date: 2007-11-05
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Publication No.: US07768848B2Publication Date: 2010-08-03
- Inventor: Keith A. Jenkins , Kevin G. Stawiasz
- Applicant: Keith A. Jenkins , Kevin G. Stawiasz
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Fleit Gibbons Gutman Bongini & Bianco P.L.
- Agent Jon A. Gibbons
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A circuit, method, and computer readable medium for on-chip measuring of noise margins in a memory device memory device are disclosed. The on-chip method includes electrically coupling at least a first circuit to a memory cell. A voltage divider is electrically coupled to at least a first voltage and a second voltage. A multiplexer circuit is electrically coupled to the voltage divider. The multiplexer selects one of the first voltage and second voltage for producing a test voltage. A selecting line is electrically coupled to a force\measure network. A comparator is coupled to the force\measure network. The force-measure network supplies the test voltage to the comparator and a measured voltage to the comparator for determining when the measured voltage exceeds the test voltage.
Public/Granted literature
- US20090116325A1 ON-CHIP CHARACTERIZATION OF NOISE-MARGINS FOR MEMORY ARRAYS Public/Granted day:2009-05-07
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