Invention Grant
- Patent Title: System for bitcell and column testing in SRAM
- Patent Title (中): SRAM中的位元和列测试系统
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Application No.: US12115122Application Date: 2008-05-05
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Publication No.: US07768850B2Publication Date: 2010-08-03
- Inventor: Aswin N. Mehta
- Applicant: Aswin N. Mehta
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Mirna Abyad; Wade J. Brady III; Frederick J. Telecky, Jr.
- Main IPC: G11C29/00
- IPC: G11C29/00
Abstract:
A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.
Public/Granted literature
- US20080273408A1 SYSTEM FOR BITCELL AND COLUMN TESTING IN SRAM Public/Granted day:2008-11-06
Information query
