A precharge circuit in a semiconductor memory apparatus includes a burst setting unit for controlling a state of a burst setting signal using delay elements in response to a burst start signal, wherein the delay elements operate in synchronization with a clock signal when the burst setting signal is deactivated, a burst termination unit for generating a burst termination signal in response to the burst setting signal, a precharge control unit for generating a read precharge control signal and a write precharge control signal in response to the burst termination signal, and a precharge signal generating unit for generating a precharge signal using the read precharge control signal or the write precharge control signal according to a read or write operation.