发明授权
US07769950B2 Cached memory system and cache controller for embedded digital signal processor
有权
用于嵌入式数字信号处理器的缓存存储系统和缓存控制器
- 专利标题: Cached memory system and cache controller for embedded digital signal processor
- 专利标题(中): 用于嵌入式数字信号处理器的缓存存储系统和缓存控制器
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申请号: US10807648申请日: 2004-03-24
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公开(公告)号: US07769950B2公开(公告)日: 2010-08-03
- 发明人: Gilbert Christopher Sih , Charles E. Sakamaki , De D. Hsu , Jian Wei , Richard Higgins
- 申请人: Gilbert Christopher Sih , Charles E. Sakamaki , De D. Hsu , Jian Wei , Richard Higgins
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM Incorporated
- 当前专利权人: QUALCOMM Incorporated
- 当前专利权人地址: US CA San Diego
- 代理商 Peter M. Kamarchik; Nicholas J. Pauley; Sam Talpalatsky
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.