Invention Grant
- Patent Title: Data processing apparatus and method for accelerating execution of subgraphs
- Patent Title (中): 用于加速执行子图的数据处理装置和方法
-
Application No.: US11884362Application Date: 2005-06-22
-
Publication No.: US07769982B2Publication Date: 2010-08-03
- Inventor: Sami Yehia , Krisztian Flautner
- Applicant: Sami Yehia , Krisztian Flautner
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- International Application: PCT/GB2005/002453 WO 20050622
- International Announcement: WO2006/136764 WO 20061228
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/318

Abstract:
A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computational subgraph has a number of input operands and produces one or more output operands. The apparatus comprises an operand store for storing the input and output operands, and processing logic for executing individual program instructions from the program. Also provided is configurable accelerator logic which, in response to reaching an execution point within the program corresponding to a sequence of individual program instructions corresponding to a computational subgraph, evaluates one or more output functions associated with the computational subgraph. The evaluation of each output function generates an output operand for storing in the operand store, and each output operand corresponds to an output that would have been generated had the sequence of individual program instructions corresponding to the computational subgraph have been executed by the processing logic. Configuration storage stores a single look-up table (LUT) configuration for each output function, and for each output function to be evaluated, the accelerator logic is configured dependent on the associated single LUT configuration from the configuration storage, such that on receipt of the input operands of the computational subgraph, the accelerator logic will generate the output operand. This technique has been found to provide a particularly efficient accelerator logic for evaluating output functions associated with computational subgraphs.
Public/Granted literature
- US20080263332A1 Data Processing Apparatus and Method for Accelerating Execution Subgraphs Public/Granted day:2008-10-23
Information query