Invention Grant
- Patent Title: Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information
- Patent Title (中): 使用基本块向量和飞越向量包括微架构依赖信息来评估集成电路设计模型性能的方法和装置
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Application No.: US12026141Application Date: 2008-02-05
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Publication No.: US07770140B2Publication Date: 2010-08-03
- Inventor: Robert H. Bell , Thomas W. Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
- Applicant: Robert H. Bell , Thomas W. Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Diana Gerhardt; Mark P Kahler
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method. Designers use the test system with test application sampling software to evaluate IC design models by using the representative test application software program.
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