Invention Grant
- Patent Title: Modeling power management for an integrated circuit
- Patent Title (中): 为集成电路建模电源管理
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Application No.: US11929517Application Date: 2007-10-30
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Publication No.: US07770142B1Publication Date: 2010-08-03
- Inventor: Arik Shmayovitsh , John Decker , Dan Leibovich
- Applicant: Arik Shmayovitsh , John Decker , Dan Leibovich
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining a testbench for simulating the IC and a verification plan for evaluating simulation results; using the testbench to simulate variations in power levels of the power domains of the IC; and using the verification plan to evaluate the simulation results for the power domains of the IC.
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