Invention Grant
- Patent Title: Semiconductor device pattern creation method, pattern data processing program, and semiconductor device manufacturing method
- Patent Title (中): 半导体器件图案生成方法,图案数据处理程序和半导体器件制造方法
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Application No.: US11474297Application Date: 2006-06-26
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Publication No.: US07770145B2Publication Date: 2010-08-03
- Inventor: Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
- Applicant: Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2005-186311 20050627
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.
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