Invention Grant
US07770147B1 Automatic generators for verilog programming 有权
用于verilog编程的自动生成器

Automatic generators for verilog programming
Abstract:
A method for generating hardware description language source files is provided. The method includes extracting an input/output (I/O) list and building a port list declaration file from the I/O list. The method also includes building a default instantiation file according to renaming rules and interpreting coding constructs to determine both variable types and sizes. The method further includes generating a sensitivity list.
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