Invention Grant
- Patent Title: Automatic generators for verilog programming
- Patent Title (中): 用于verilog编程的自动生成器
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Application No.: US11234623Application Date: 2005-09-22
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Publication No.: US07770147B1Publication Date: 2010-08-03
- Inventor: Marc Spitzer , John Packer
- Applicant: Marc Spitzer , John Packer
- Applicant Address: US CA Milpitas
- Assignee: Adaptec, Inc.
- Current Assignee: Adaptec, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Martin Penilla & Gencarella, LLP
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F9/45

Abstract:
A method for generating hardware description language source files is provided. The method includes extracting an input/output (I/O) list and building a port list declaration file from the I/O list. The method also includes building a default instantiation file according to renaming rules and interpreting coding constructs to determine both variable types and sizes. The method further includes generating a sensitivity list.
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