Invention Grant
- Patent Title: Structures for testing and locating defects in integrated circuits
- Patent Title (中): 用于测试和定位集成电路缺陷的结构
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Application No.: US12037687Application Date: 2008-02-26
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Publication No.: US07772867B2Publication Date: 2010-08-10
- Inventor: Richard L. Guldi , Toan Tran , Deepak A. Ramappa
- Applicant: Richard L. Guldi , Toan Tran , Deepak A. Ramappa
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G01R31/02
- IPC: G01R31/02

Abstract:
A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.
Public/Granted literature
- US20090212793A1 STRUCTURES FOR TESTING AND LOCATING DEFECTS IN INTEGRATED CIRCUITS Public/Granted day:2009-08-27
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