发明授权
US07772878B2 Parallel resistor circuit, on-die termination device having the same, and semiconductor memory device having the on-die termination device
有权
并联电阻电路，具有其的片上端接装置和具有片上终端装置的半导体存储器件
- 专利标题： Parallel resistor circuit, on-die termination device having the same, and semiconductor memory device having the on-die termination device
- 专利标题（中）： 并联电阻电路，具有其的片上端接装置和具有片上终端装置的半导体存储器件
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申请号： US12346816申请日： 2008-12-30
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公开(公告)号： US07772878B2公开(公告)日： 2010-08-10
- 发明人: Chang-Kyu Choi
- 申请人： Chang-Kyu Choi
- 申请人地址： KR Gyeonggi-do
- 专利权人： Hynix Semiconductor, Inc.
- 当前专利权人： Hynix Semiconductor, Inc.
- 当前专利权人地址： KR Gyeonggi-do
- 代理机构： IP & T Law Firm PLC
- 优先权： KR10-2008-0063123 20080630
- 主分类号： H03K19/003
- IPC分类号： H03K19/003
摘要：
A parallel resistor circuit that can reduce an error of a resistance value, an on-die termination having the same, and a semiconductor device having the on-die termination device. The semiconductor memory device includes a calibration circuit configured to pull up or pull down a predetermined node and compare a voltage of the predetermined node with a reference voltage to generate calibration codes, by using parallel resistor units that are turned on or off in response to the calibration codes. An output driver is configured to terminate a data output node to a pull-up or pull-down level to output data, by using the parallel resistor units. At least one of the parallel resistor units having at least two resistivities includes resistors with different resistivities connected to each other in parallel.
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