Invention Grant
- Patent Title: Systems and methods for dynamic logic keeper optimization
- Patent Title (中): 用于动态逻辑门控器优化的系统和方法
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Application No.: US11869785Application Date: 2007-10-10
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Publication No.: US07772890B2Publication Date: 2010-08-10
- Inventor: Andrew Marshall
- Applicant: Andrew Marshall
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03K19/096
- IPC: H03K19/096

Abstract:
Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic devices with a logic circuit that includes an inverting output buffer, a logic function, a bias transistor, and a current circuit. An input of the logic function is electrically coupled to a logic input, an output of the logic function is electrically coupled to an input of the inverting output buffer, and the logic function exhibits a leakage current. The gate of the bias transistor is electrically coupled to an output of the inverting buffer, and a first leg of the bias transistor is electrically coupled to the input of the inverting buffer. The current circuit supplies a current corresponding to the to a second leg of the bias transistor. In some cases, an improved performance may be achieved for a given leakage, or a reduced leakage may be achieved for a given performance.
Public/Granted literature
- US20090096485A1 Systems and Methods for Dynamic Logic Keeper Optimization Public/Granted day:2009-04-16
Information query
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