Invention Grant
US07773438B2 Integrated circuit that stores first and second defective memory cell addresses
有权
存储第一和第二有缺陷的存储单元地址的集成电路
- Patent Title: Integrated circuit that stores first and second defective memory cell addresses
- Patent Title (中): 存储第一和第二有缺陷的存储单元地址的集成电路
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Application No.: US12134485Application Date: 2008-06-06
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Publication No.: US07773438B2Publication Date: 2010-08-10
- Inventor: Khaled Fekih-Romdhane
- Applicant: Khaled Fekih-Romdhane
- Applicant Address: US NC Cary
- Assignee: Qimonda North America Corp.
- Current Assignee: Qimonda North America Corp.
- Current Assignee Address: US NC Cary
- Agency: Dicke, Billig & Czaja P.L.L.C.
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
An integrated circuit including an array of memory cells, volatile storage, non-volatile storage and a circuit. The circuit is configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sense first addresses. The circuit detects second defective memory cells via the sense first addresses and stores second addresses of the second defective memory cells in the volatile storage and in the non-volatile storage.
Public/Granted literature
- US20090303813A1 INTEGRATED CIRCUIT THAT STORES FIRST AND SECOND DEFECTIVE MEMORY CELL ADDRESSES Public/Granted day:2009-12-10
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