发明授权
US07776732B2 Metal high-K transistor having silicon sidewall for reduced parasitic capacitance, and process to fabricate same
失效
具有用于降低寄生电容的硅侧壁的金属高K晶体管，以及制造相同的工艺
- 专利标题： Metal high-K transistor having silicon sidewall for reduced parasitic capacitance, and process to fabricate same
- 专利标题（中）： 具有用于降低寄生电容的硅侧壁的金属高K晶体管，以及制造相同的工艺
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申请号： US11852359申请日： 2007-09-10
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公开(公告)号： US07776732B2公开(公告)日： 2010-08-17
- 发明人: Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
- 申请人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Harrington & Smith
- 主分类号： H01L21/3205
- IPC分类号： H01L21/3205 ; H01L21/4763 ; H01L29/78
摘要：
A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.
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