发明授权
US07777330B2 High bandwidth cache-to-processing unit communication in a multiple processor/cache system
有权
在多处理器/高速缓存系统中的高带宽高速缓存到处理单元通信
- 专利标题： High bandwidth cache-to-processing unit communication in a multiple processor/cache system
- 专利标题（中）： 在多处理器/高速缓存系统中的高带宽高速缓存到处理单元通信
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申请号： US12026325申请日： 2008-02-05
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公开(公告)号： US07777330B2公开(公告)日： 2010-08-17
- 发明人: Perry H. Pelley , Michael B. McShane
- 申请人： Perry H. Pelley , Michael B. McShane
- 申请人地址： US TX Austin
- 专利权人： Freescale Semiconductor, Inc.
- 当前专利权人： Freescale Semiconductor, Inc.
- 当前专利权人地址： US TX Austin
- 主分类号： H01L23/34
- IPC分类号： H01L23/34
摘要：
A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.
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