发明授权
- 专利标题: Delay adjusting circuit and control method of the same
- 专利标题(中): 延时调整电路及其控制方法相同
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申请号: US11882788申请日: 2007-08-06
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公开(公告)号: US07777539B2公开(公告)日: 2010-08-17
- 发明人: Shigetaka Asano
- 申请人: Shigetaka Asano
- 申请人地址: JP Yokohama
- 专利权人: Fujitsu Semiconductor Limited
- 当前专利权人: Fujitsu Semiconductor Limited
- 当前专利权人地址: JP Yokohama
- 代理机构: Arent Fox LLP
- 优先权: JP2006-216587 20060809
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A delay adjusting circuit including a delay part in which delay elements of n+1 (n≧2) stages are connected to each other in series, a first phase comparator for detecting whether a first edge that is a transition edge of a signal of an n−1-th stage of the delay part from a first logic level to a second logic level advances from a first reference signal edge that is a transition edge of a first reference signal from the first logic level to the second logic level, a second phase comparator for detecting whether a second edge that is a transition edge of a signal of an n+1-th stage of the delay part from the first logic level to the second logic level delays from the first reference signal edge, and a delay element adjusting part that corrects a second reference signal so that the first edge advances from the first reference signal edge in the first phase comparator and the second edge delays from the first reference signal edge in the second phase comparator, and that outputs a reference bias signal for adjusting delay times of the delay elements of the delay part.
公开/授权文献
- US20080036515A1 Delay adjusting circuit and control method of the same 公开/授权日:2008-02-14
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