发明授权
- 专利标题: Deinterleaver and dual-viterbi decoder architecture
- 专利标题(中): 去交织器和双维特比解码器架构
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申请号: US11490844申请日: 2006-07-21
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公开(公告)号: US07779338B2公开(公告)日: 2010-08-17
- 发明人: Mustafa Altintas , Turgut Aytur , Ravishankar H. Mahadevappa , Feng Shi , Stephan ten Brink , Ran Yan
- 申请人: Mustafa Altintas , Turgut Aytur , Ravishankar H. Mahadevappa , Feng Shi , Stephan ten Brink , Ran Yan
- 申请人地址: TW Hsinchu
- 专利权人: Realtek Semiconductor Corp.
- 当前专利权人: Realtek Semiconductor Corp.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Thomas, Kayden, Horstemeyer & Risley, LLP
- 主分类号: H03M13/03
- IPC分类号: H03M13/03
摘要:
Pairs of parallel Viterbi decoders use windowed block data for decoding data at rates above 320 Mbps. Memory banks of the deinterleavers feeding the decoders operate such that some are receiving data while others are sending data to the decoders. Parallel input streams to every pair of decoders overlap for several traceback lengths of the decoder causing data input to a first decoder at the end of an input stream to be the same as the data input to a second decoder of the same pair at the beginning of an input stream. Then, the first decoder is able to post-synchronize its path metric with the second decoder and the second decoder is able to pre-synchronize its path metric with the first. Either, the deinterleaver data length is an integer multiple of the traceback length or the data input to only the first block of the first interleaver is padded.
公开/授权文献
- US20070067704A1 Deinterleaver and dual-viterbi decoder architecture 公开/授权日:2007-03-22
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