发明授权
US07793025B2 Hardware managed context sensitive interrupt priority level control
有权
硬件管理上下文敏感中断优先级控制
- 专利标题: Hardware managed context sensitive interrupt priority level control
- 专利标题(中): 硬件管理上下文敏感中断优先级控制
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申请号: US12057989申请日: 2008-03-28
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公开(公告)号: US07793025B2公开(公告)日: 2010-09-07
- 发明人: Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
- 申请人: Robert Ehrlich , Brett W. Murdock , Craig D. Shaw
- 申请人地址: US TX Austin
- 专利权人: Freescale Semiconductor, Inc.
- 当前专利权人: Freescale Semiconductor, Inc.
- 当前专利权人地址: US TX Austin
- 代理机构: Hamilton & Terrile, LLP
- 代理商 Michael Rocco Cannatti
- 主分类号: G06F13/14
- IPC分类号: G06F13/14 ; G06F13/26
摘要:
A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.
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