Invention Grant
- Patent Title: Method for manufacturing stack package using through-electrodes
- Patent Title (中): 使用通孔制造堆叠封装的方法
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Application No.: US12345858Application Date: 2008-12-30
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Publication No.: US07795073B2Publication Date: 2010-09-14
- Inventor: Kwon Whan Han , Chang Jun Park , Seong Cheol Kim , Sung Min Kim , Hyeong Seok Choi , Ha Na Lee
- Applicant: Kwon Whan Han , Chang Jun Park , Seong Cheol Kim , Sung Min Kim , Hyeong Seok Choi , Ha Na Lee
- Applicant Address: KR Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Ladas & Parry LLP
- Priority: KR10-2008-0010470 20080201; KR10-2008-0103086 20081021
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50

Abstract:
Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.
Public/Granted literature
- US20090197372A1 METHOD FOR MANUFACTURING STACK PACKAGE USING THROUGH-ELECTRODES Public/Granted day:2009-08-06
Information query
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