发明授权
- 专利标题： Voltage step-down circuit
- 专利标题（中）： 电压降压电路
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申请号： US12051465申请日： 2008-03-19
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公开(公告)号： US07795953B2公开(公告)日： 2010-09-14
- 发明人: Ryu Ogiwara , Shinichiro Shiratake , Daisaburo Takashima
- 申请人： Ryu Ogiwara , Shinichiro Shiratake , Daisaburo Takashima
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权： JP2007-073448 20070320
- 主分类号： G05F1/10
- IPC分类号： G05F1/10
摘要：
According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.
公开/授权文献
- US20080231351A1 VOLTAGE STEP-DOWN CIRCUIT 公开/授权日：2008-09-25
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