发明授权
US07805690B2 Method for generating compiler, simulation, synthesis and test suite from a common processor specification 有权
从通用处理器规范生成编译器,仿真,综合和测试套件的方法

  • 专利标题: Method for generating compiler, simulation, synthesis and test suite from a common processor specification
  • 专利标题(中): 从通用处理器规范生成编译器,仿真,综合和测试套件的方法
  • 申请号: US11865596
    申请日: 2007-10-01
  • 公开(公告)号: US07805690B2
    公开(公告)日: 2010-09-28
  • 发明人: John Willis
  • 申请人: John Willis
  • 申请人地址: US MN Rochester
  • 专利权人: FTL Systems, Inc.
  • 当前专利权人: FTL Systems, Inc.
  • 当前专利权人地址: US MN Rochester
  • 代理机构: Ojanen Law Offices
  • 代理商 Craig J. Lervick; Karuna Ojanen
  • 主分类号: G06F17/50
  • IPC分类号: G06F17/50
Method for generating compiler, simulation, synthesis and test suite from a common processor specification
摘要:
A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target a FPGA, ASIC, system-on-a-chip or custom logic. It analyzes behavior of the embedded binaries running on processing units and implementations augmented by additional physical technology and parameters, yielding a more detailed prediction of the resulting hardware/software system behavior when realized through manufacturing.
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