发明授权
- 专利标题: PLL circuit
- 专利标题(中): PLL电路
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申请号: US11993108申请日: 2007-03-29
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公开(公告)号: US07808326B2公开(公告)日: 2010-10-05
- 发明人: Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada , Junji Nakatsuka
- 申请人: Kazuaki Sogawa , Masayoshi Kinoshita , Yuji Yamada , Junji Nakatsuka
- 申请人地址: JP Osaka
- 专利权人: Panasonic Corporation
- 当前专利权人: Panasonic Corporation
- 当前专利权人地址: JP Osaka
- 代理机构: McDermott Will & Emery LLP
- 优先权: JP2006-279165 20061012
- 国际申请: PCT/JP2007/056817 WO 20070329
- 国际公布: WO2008/044350 WO 20080417
- 主分类号: H03L7/00
- IPC分类号: H03L7/00
摘要:
In a PLL circuit, a voltage controlled oscillator 4 has two voltage-current conversion circuits 40 and 41 and a selection circuit 42 for selecting an output of either one of the voltage-current conversion circuits 40 and 41. The output of the voltage-current conversion circuit selected by the selection circuit 42 is inputted to a current controlled oscillator 45. The one voltage-current conversion circuit 41 has an input thereof connected to an output of a loop filter 3, while the other voltage-current conversion circuit 40 has an input thereof connected to an input terminal 8 for evaluating the oscillation characteristics of the voltage controlled oscillator 4. As a result, time-varying fluctuations in the voltage of the loop filter resulting from a structure in which the input terminal for evaluating the oscillation characteristics of the voltage controlled oscillator is connected to the loop filter via a switch and time-varying fluctuations in the output frequency of the PLL circuit are effectively suppressed.
公开/授权文献
- US20090295489A1 PLL CIRCUIT 公开/授权日:2009-12-03
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