Systems and methods for performing bit loading in a dual latency data transmission system. In a computer network, such as an XDSL-based network, carrier channels are allocated between two latency paths. Error sensitive information is transmitted over a latency path employing one or more forward error correction techniques. Latency sensitive information that is relatively more tolerant of errors is transmitted over the other latency path. Rather than employing the lowest coding gain for carrier channels having the two different latency paths, the highest coding gain for each path is used by applying different target S-N-R margins for carrier channels having different latency paths.