A processor for performing a Fast Fourier Transform and/or an Inverse Fast Fourier Transform of a complex input signal comprises a first stage for passing the input signal to a second stage when a Fast Fourier Transform procedure is to be performed and for swapping the real and imaginary components of the complex input signal before passing the signal to the second stage if an Inverse Fast Fourier Transform procedure is to be performed. The second stage has first and second radix-4 butterfly elements. A third stage is arranged to switch between first and second operating modes, the second operating mode being for processing a complex conjugate symmetrical input signal. A fourth stage has a plurality of processing units, one or more of the processing units comprising a radix-2 pipelined Fast Fourier Transform processor. The first and second radix-4 butterfly elements are arranged to perform a butterfly operation on the complex input signal to generate and deliver one or more components of a processed signal to the fourth stage. The fourth stage is arranged to process the processed signal received from the first stage according to a Fast Fourier Transform processing procedure to produce an output signal. There is also disclosed a method for performing a Fast Fourier Transform and/or Inverse Fast Fourier Transform of a complex input signal.