Invention Grant
US07824825B2 Stencil masks, method of manufacturing stencil masks, and method of using stencil masks
失效
模板掩模,制造模板掩模的方法以及使用模板掩模的方法
- Patent Title: Stencil masks, method of manufacturing stencil masks, and method of using stencil masks
- Patent Title (中): 模板掩模,制造模板掩模的方法以及使用模板掩模的方法
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Application No.: US11496552Application Date: 2006-08-01
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Publication No.: US07824825B2Publication Date: 2010-11-02
- Inventor: Tsuyoshi Nishiwaki , Hideki Tojima
- Applicant: Tsuyoshi Nishiwaki , Hideki Tojima
- Applicant Address: JP Toyota-shi, Aichi-ken
- Assignee: Toyota Jidosha Kabushiki Kaisha
- Current Assignee: Toyota Jidosha Kabushiki Kaisha
- Current Assignee Address: JP Toyota-shi, Aichi-ken
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
- Priority: JP2005-225453 20050803
- Main IPC: G03F1/00
- IPC: G03F1/00 ; G03F7/20 ; G21K5/04

Abstract:
The present invention presents a stencil mask in which various surface patterns can be formed, and in which deformation is suppressed when charged particles are introduced. A stencil mask of the present invention is provided with a semiconductor stack. A first penetrating hole corresponding to an ion introducing area is formed in a first semiconductor layer of the semiconductor stack, and second penetrating holes are formed in a second semiconductor layer, these second penetrating holes having a width greater than the width of the first penetrating hole. The first penetrating hole and the second penetrating holes communicate and pass through the semiconductor stack. Beam members extending between adjacent second penetrating holes connect portions of the first semiconductor layer separated by the first penetrating hole.
Public/Granted literature
- US20070077501A1 Stencil masks, method of manufacturing stencil masks, and method of using stencil masks Public/Granted day:2007-04-05
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