Invention Grant
- Patent Title: Method of integrated circuit fabrication
- Patent Title (中): 集成电路制造方法
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Application No.: US12021806Application Date: 2008-01-29
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Publication No.: US07824962B2Publication Date: 2010-11-02
- Inventor: Franco Mariani , Werner Kroeninger
- Applicant: Franco Mariani , Werner Kroeninger
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A method for fabricating an integrated circuit including forming a first trench in a rear side of a semiconductor wafer, wherein the first trench has a depth extending partially through a thickness of the semiconductor wafer, coating the rear side with a layer of coating material, including filling the first trench with the coating material, and forming a second trench in a front side of the semiconductor wafer, wherein the second trench is aligned with and has a width less than a width of the first trench, and wherein the second trench has a depth extending at least through a remaining portion of the semiconductor wafer so as to be in communication with the coating material filling the first trench.
Public/Granted literature
- US20090189258A1 METHOD OF INTEGRATED CIRCUIT FABRICATION Public/Granted day:2009-07-30
Information query
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