Invention Grant
US07824965B2 Near chip scale package integration process 有权
近芯片级封装集成过程

Near chip scale package integration process
Abstract:
Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.
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